;buildInfoPackage: chisel3, version: 3.4.3, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit SimTop : 
  module InstFetch : 
    input clock : Clock
    input reset : Reset
    output io : {imem : {en : UInt<1>, addr : UInt<64>, flip rdata : UInt<64>}, pc : UInt<32>, inst : UInt<32>}
    
    reg pc_en : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[InstFetch.scala 11:22]
    pc_en <= UInt<1>("h01") @[InstFetch.scala 12:9]
    reg pc : UInt<32>, clock with : (reset => (reset, UInt<32>("h080000000"))) @[InstFetch.scala 14:19]
    node _pc_T = add(pc, UInt<3>("h04")) @[InstFetch.scala 15:12]
    node _pc_T_1 = tail(_pc_T, 1) @[InstFetch.scala 15:12]
    pc <= _pc_T_1 @[InstFetch.scala 15:6]
    io.imem.en <= UInt<1>("h01") @[InstFetch.scala 17:14]
    io.imem.addr <= pc @[InstFetch.scala 18:16]
    node _io_pc_T = mux(pc_en, pc, UInt<1>("h00")) @[InstFetch.scala 20:15]
    io.pc <= _io_pc_T @[InstFetch.scala 20:9]
    node _io_inst_T = bits(io.imem.rdata, 31, 0) @[InstFetch.scala 21:38]
    node _io_inst_T_1 = mux(pc_en, _io_inst_T, UInt<1>("h00")) @[InstFetch.scala 21:17]
    io.inst <= _io_inst_T_1 @[InstFetch.scala 21:11]
    
  module Decode : 
    input clock : Clock
    input reset : Reset
    output io : {flip inst : UInt<32>, rs1_addr : UInt<5>, rs1_en : UInt<1>, rs2_addr : UInt<5>, rs2_en : UInt<1>, rd_addr : UInt<5>, rd_en : UInt<1>, opcode : UInt<8>, imm : UInt<64>}
    
    wire opcode : UInt<8>
    opcode <= UInt<1>("h00")
    node _imm_i_T = bits(io.inst, 31, 31) @[Decode.scala 20:32]
    node _imm_i_T_1 = bits(_imm_i_T, 0, 0) @[Bitwise.scala 72:15]
    node imm_i_hi = mux(_imm_i_T_1, UInt<53>("h01fffffffffffff"), UInt<53>("h00")) @[Bitwise.scala 72:12]
    node imm_i_lo = bits(io.inst, 30, 20) @[Decode.scala 20:43]
    node imm_i = cat(imm_i_hi, imm_i_lo) @[Cat.scala 30:58]
    node _T = and(io.inst, UInt<15>("h0707f")) @[Decode.scala 23:14]
    node _T_1 = eq(UInt<5>("h013"), _T) @[Decode.scala 23:14]
    when _T_1 : @[Decode.scala 23:24]
      opcode <= UInt<1>("h01") @[Decode.scala 24:12]
      skip @[Decode.scala 23:24]
    node _io_rs1_addr_T = bits(io.inst, 19, 15) @[Decode.scala 27:22]
    io.rs1_addr <= _io_rs1_addr_T @[Decode.scala 27:15]
    node _io_rs2_addr_T = bits(io.inst, 24, 20) @[Decode.scala 28:22]
    io.rs2_addr <= _io_rs2_addr_T @[Decode.scala 28:15]
    node _io_rd_addr_T = bits(io.inst, 11, 7) @[Decode.scala 29:21]
    io.rd_addr <= _io_rd_addr_T @[Decode.scala 29:14]
    io.rs1_en <= UInt<1>("h00") @[Decode.scala 31:13]
    io.rs2_en <= UInt<1>("h00") @[Decode.scala 32:13]
    io.rd_en <= UInt<1>("h00") @[Decode.scala 33:12]
    node _T_2 = and(io.inst, UInt<15>("h0707f")) @[Decode.scala 35:14]
    node _T_3 = eq(UInt<5>("h013"), _T_2) @[Decode.scala 35:14]
    when _T_3 : @[Decode.scala 35:24]
      io.rs1_en <= UInt<1>("h01") @[Decode.scala 36:15]
      io.rs2_en <= UInt<1>("h00") @[Decode.scala 37:15]
      io.rd_en <= UInt<1>("h01") @[Decode.scala 38:14]
      skip @[Decode.scala 35:24]
    io.opcode <= opcode @[Decode.scala 41:13]
    io.imm <= imm_i @[Decode.scala 42:10]
    
  extmodule DifftestArchIntRegState : 
    input clock : Clock
    input coreid : UInt<8>
    input gpr : UInt<64>[32]
    
    defname = DifftestArchIntRegState
    
    
  module RegFile : 
    input clock : Clock
    input reset : Reset
    output io : {flip rs1_addr : UInt<5>, flip rs2_addr : UInt<5>, rs1_data : UInt<64>, rs2_data : UInt<64>, flip rd_addr : UInt<5>, flip rd_data : UInt<64>, flip rd_en : UInt<1>}
    
    wire _rf_WIRE : UInt<64>[32] @[RegFile.scala 16:27]
    _rf_WIRE[0] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[1] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[2] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[3] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[4] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[5] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[6] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[7] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[8] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[9] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[10] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[11] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[12] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[13] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[14] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[15] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[16] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[17] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[18] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[19] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[20] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[21] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[22] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[23] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[24] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[25] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[26] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[27] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[28] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[29] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[30] <= UInt<64>("h00") @[RegFile.scala 16:27]
    _rf_WIRE[31] <= UInt<64>("h00") @[RegFile.scala 16:27]
    reg rf : UInt<64>[32], clock with : (reset => (reset, _rf_WIRE)) @[RegFile.scala 16:19]
    node _T = neq(io.rd_addr, UInt<1>("h00")) @[RegFile.scala 18:33]
    node _T_1 = and(io.rd_en, _T) @[RegFile.scala 18:18]
    when _T_1 : @[RegFile.scala 18:43]
      rf[io.rd_addr] <= io.rd_data @[RegFile.scala 19:20]
      skip @[RegFile.scala 18:43]
    node _io_rs1_data_T = neq(io.rs1_addr, UInt<1>("h00")) @[RegFile.scala 22:35]
    node _io_rs1_data_T_1 = mux(_io_rs1_data_T, rf[io.rs1_addr], UInt<1>("h00")) @[RegFile.scala 22:21]
    io.rs1_data <= _io_rs1_data_T_1 @[RegFile.scala 22:15]
    node _io_rs2_data_T = neq(io.rs2_addr, UInt<1>("h00")) @[RegFile.scala 23:35]
    node _io_rs2_data_T_1 = mux(_io_rs2_data_T, rf[io.rs2_addr], UInt<1>("h00")) @[RegFile.scala 23:21]
    io.rs2_data <= _io_rs2_data_T_1 @[RegFile.scala 23:15]
    inst dt_ar of DifftestArchIntRegState @[RegFile.scala 25:21]
    dt_ar.gpr is invalid
    dt_ar.coreid is invalid
    dt_ar.clock is invalid
    dt_ar.clock <= clock @[RegFile.scala 26:19]
    dt_ar.coreid <= UInt<1>("h00") @[RegFile.scala 27:19]
    dt_ar.gpr[0] <= rf[0] @[RegFile.scala 28:19]
    dt_ar.gpr[1] <= rf[1] @[RegFile.scala 28:19]
    dt_ar.gpr[2] <= rf[2] @[RegFile.scala 28:19]
    dt_ar.gpr[3] <= rf[3] @[RegFile.scala 28:19]
    dt_ar.gpr[4] <= rf[4] @[RegFile.scala 28:19]
    dt_ar.gpr[5] <= rf[5] @[RegFile.scala 28:19]
    dt_ar.gpr[6] <= rf[6] @[RegFile.scala 28:19]
    dt_ar.gpr[7] <= rf[7] @[RegFile.scala 28:19]
    dt_ar.gpr[8] <= rf[8] @[RegFile.scala 28:19]
    dt_ar.gpr[9] <= rf[9] @[RegFile.scala 28:19]
    dt_ar.gpr[10] <= rf[10] @[RegFile.scala 28:19]
    dt_ar.gpr[11] <= rf[11] @[RegFile.scala 28:19]
    dt_ar.gpr[12] <= rf[12] @[RegFile.scala 28:19]
    dt_ar.gpr[13] <= rf[13] @[RegFile.scala 28:19]
    dt_ar.gpr[14] <= rf[14] @[RegFile.scala 28:19]
    dt_ar.gpr[15] <= rf[15] @[RegFile.scala 28:19]
    dt_ar.gpr[16] <= rf[16] @[RegFile.scala 28:19]
    dt_ar.gpr[17] <= rf[17] @[RegFile.scala 28:19]
    dt_ar.gpr[18] <= rf[18] @[RegFile.scala 28:19]
    dt_ar.gpr[19] <= rf[19] @[RegFile.scala 28:19]
    dt_ar.gpr[20] <= rf[20] @[RegFile.scala 28:19]
    dt_ar.gpr[21] <= rf[21] @[RegFile.scala 28:19]
    dt_ar.gpr[22] <= rf[22] @[RegFile.scala 28:19]
    dt_ar.gpr[23] <= rf[23] @[RegFile.scala 28:19]
    dt_ar.gpr[24] <= rf[24] @[RegFile.scala 28:19]
    dt_ar.gpr[25] <= rf[25] @[RegFile.scala 28:19]
    dt_ar.gpr[26] <= rf[26] @[RegFile.scala 28:19]
    dt_ar.gpr[27] <= rf[27] @[RegFile.scala 28:19]
    dt_ar.gpr[28] <= rf[28] @[RegFile.scala 28:19]
    dt_ar.gpr[29] <= rf[29] @[RegFile.scala 28:19]
    dt_ar.gpr[30] <= rf[30] @[RegFile.scala 28:19]
    dt_ar.gpr[31] <= rf[31] @[RegFile.scala 28:19]
    
  module Execution : 
    input clock : Clock
    input reset : Reset
    output io : {flip opcode : UInt<8>, flip in1 : UInt<64>, flip in2 : UInt<64>, out : UInt<64>, dmem : {en : UInt<1>, addr : UInt<64>, flip rdata : UInt<64>, wdata : UInt<64>, wmask : UInt<64>, wen : UInt<1>}}
    
    io.out <= UInt<1>("h00") @[Execution.scala 13:10]
    node _T = eq(io.opcode, UInt<1>("h01")) @[Execution.scala 16:19]
    when _T : @[Execution.scala 16:28]
      node _io_out_T = add(io.in1, io.in2) @[Execution.scala 17:22]
      node _io_out_T_1 = tail(_io_out_T, 1) @[Execution.scala 17:22]
      io.out <= _io_out_T_1 @[Execution.scala 17:12]
      skip @[Execution.scala 16:28]
    io.dmem.en <= UInt<1>("h00") @[Execution.scala 20:14]
    io.dmem.addr <= UInt<1>("h00") @[Execution.scala 21:16]
    io.dmem.wen <= UInt<1>("h00") @[Execution.scala 22:15]
    io.dmem.wdata <= UInt<1>("h00") @[Execution.scala 23:17]
    io.dmem.wmask <= UInt<1>("h00") @[Execution.scala 24:17]
    
  extmodule DifftestInstrCommit : 
    input clock : Clock
    input coreid : UInt<8>
    input index : UInt<8>
    input valid : UInt<1>
    input pc : UInt<64>
    input instr : UInt<32>
    input special : UInt<8>
    input skip : UInt<1>
    input isRVC : UInt<1>
    input scFailed : UInt<1>
    input wen : UInt<1>
    input wdata : UInt<64>
    input wdest : UInt<8>
    
    defname = DifftestInstrCommit
    
    
  extmodule DifftestArchEvent : 
    input clock : Clock
    input coreid : UInt<8>
    input intrNO : UInt<32>
    input cause : UInt<32>
    input exceptionPC : UInt<64>
    input exceptionInst : UInt<32>
    
    defname = DifftestArchEvent
    
    
  extmodule DifftestTrapEvent : 
    input clock : Clock
    input coreid : UInt<8>
    input valid : UInt<1>
    input code : UInt<3>
    input pc : UInt<64>
    input cycleCnt : UInt<64>
    input instrCnt : UInt<64>
    
    defname = DifftestTrapEvent
    
    
  extmodule DifftestCSRState : 
    input clock : Clock
    input coreid : UInt<8>
    input priviledgeMode : UInt<2>
    input mstatus : UInt<64>
    input sstatus : UInt<64>
    input mepc : UInt<64>
    input sepc : UInt<64>
    input mtval : UInt<64>
    input stval : UInt<64>
    input mtvec : UInt<64>
    input stvec : UInt<64>
    input mcause : UInt<64>
    input scause : UInt<64>
    input satp : UInt<64>
    input mip : UInt<64>
    input mie : UInt<64>
    input mscratch : UInt<64>
    input sscratch : UInt<64>
    input mideleg : UInt<64>
    input medeleg : UInt<64>
    
    defname = DifftestCSRState
    
    
  module Core : 
    input clock : Clock
    input reset : Reset
    output io : {imem : {en : UInt<1>, addr : UInt<64>, flip rdata : UInt<64>}, dmem : {en : UInt<1>, addr : UInt<64>, flip rdata : UInt<64>, wdata : UInt<64>, wmask : UInt<64>, wen : UInt<1>}}
    
    inst fetch of InstFetch @[Core.scala 11:21]
    fetch.clock <= clock
    fetch.reset <= reset
    fetch.io.imem.rdata <= io.imem.rdata @[Core.scala 12:17]
    io.imem.addr <= fetch.io.imem.addr @[Core.scala 12:17]
    io.imem.en <= fetch.io.imem.en @[Core.scala 12:17]
    inst decode of Decode @[Core.scala 14:22]
    decode.clock <= clock
    decode.reset <= reset
    decode.io.inst <= fetch.io.inst @[Core.scala 15:18]
    inst rf of RegFile @[Core.scala 17:18]
    rf.clock <= clock
    rf.reset <= reset
    rf.io.rs1_addr <= decode.io.rs1_addr @[Core.scala 18:18]
    rf.io.rs2_addr <= decode.io.rs2_addr @[Core.scala 19:18]
    rf.io.rd_addr <= decode.io.rd_addr @[Core.scala 20:17]
    rf.io.rd_en <= decode.io.rd_en @[Core.scala 21:15]
    inst execution of Execution @[Core.scala 23:25]
    execution.clock <= clock
    execution.reset <= reset
    execution.io.opcode <= decode.io.opcode @[Core.scala 24:23]
    node _execution_io_in1_T = mux(decode.io.rs1_en, rf.io.rs1_data, UInt<1>("h00")) @[Core.scala 25:26]
    execution.io.in1 <= _execution_io_in1_T @[Core.scala 25:20]
    node _execution_io_in2_T = mux(decode.io.rs2_en, rf.io.rs2_data, decode.io.imm) @[Core.scala 26:26]
    execution.io.in2 <= _execution_io_in2_T @[Core.scala 26:20]
    io.dmem.wen <= execution.io.dmem.wen @[Core.scala 27:21]
    io.dmem.wmask <= execution.io.dmem.wmask @[Core.scala 27:21]
    io.dmem.wdata <= execution.io.dmem.wdata @[Core.scala 27:21]
    execution.io.dmem.rdata <= io.dmem.rdata @[Core.scala 27:21]
    io.dmem.addr <= execution.io.dmem.addr @[Core.scala 27:21]
    io.dmem.en <= execution.io.dmem.en @[Core.scala 27:21]
    rf.io.rd_data <= execution.io.out @[Core.scala 28:17]
    inst dt_ic of DifftestInstrCommit @[Core.scala 32:21]
    dt_ic.wdest is invalid
    dt_ic.wdata is invalid
    dt_ic.wen is invalid
    dt_ic.scFailed is invalid
    dt_ic.isRVC is invalid
    dt_ic.skip is invalid
    dt_ic.special is invalid
    dt_ic.instr is invalid
    dt_ic.pc is invalid
    dt_ic.valid is invalid
    dt_ic.index is invalid
    dt_ic.coreid is invalid
    dt_ic.clock is invalid
    dt_ic.clock <= clock @[Core.scala 33:21]
    dt_ic.coreid <= UInt<1>("h00") @[Core.scala 34:21]
    dt_ic.index <= UInt<1>("h00") @[Core.scala 35:21]
    dt_ic.valid <= UInt<1>("h01") @[Core.scala 36:21]
    reg dt_ic_io_pc_REG : UInt, clock @[Core.scala 37:31]
    dt_ic_io_pc_REG <= fetch.io.pc @[Core.scala 37:31]
    dt_ic.pc <= dt_ic_io_pc_REG @[Core.scala 37:21]
    reg dt_ic_io_instr_REG : UInt, clock @[Core.scala 38:31]
    dt_ic_io_instr_REG <= fetch.io.inst @[Core.scala 38:31]
    dt_ic.instr <= dt_ic_io_instr_REG @[Core.scala 38:21]
    dt_ic.special <= UInt<1>("h00") @[Core.scala 39:21]
    dt_ic.skip <= UInt<1>("h00") @[Core.scala 40:21]
    dt_ic.isRVC <= UInt<1>("h00") @[Core.scala 41:21]
    dt_ic.scFailed <= UInt<1>("h00") @[Core.scala 42:21]
    reg dt_ic_io_wen_REG : UInt<1>, clock @[Core.scala 43:31]
    dt_ic_io_wen_REG <= decode.io.rd_en @[Core.scala 43:31]
    dt_ic.wen <= dt_ic_io_wen_REG @[Core.scala 43:21]
    reg dt_ic_io_wdata_REG : UInt, clock @[Core.scala 44:31]
    dt_ic_io_wdata_REG <= execution.io.out @[Core.scala 44:31]
    dt_ic.wdata <= dt_ic_io_wdata_REG @[Core.scala 44:21]
    reg dt_ic_io_wdest_REG : UInt, clock @[Core.scala 45:31]
    dt_ic_io_wdest_REG <= decode.io.rd_addr @[Core.scala 45:31]
    dt_ic.wdest <= dt_ic_io_wdest_REG @[Core.scala 45:21]
    inst dt_ae of DifftestArchEvent @[Core.scala 47:21]
    dt_ae.exceptionInst is invalid
    dt_ae.exceptionPC is invalid
    dt_ae.cause is invalid
    dt_ae.intrNO is invalid
    dt_ae.coreid is invalid
    dt_ae.clock is invalid
    dt_ae.clock <= clock @[Core.scala 48:25]
    dt_ae.coreid <= UInt<1>("h00") @[Core.scala 49:25]
    dt_ae.intrNO <= UInt<1>("h00") @[Core.scala 50:25]
    dt_ae.cause <= UInt<1>("h00") @[Core.scala 51:25]
    dt_ae.exceptionPC <= UInt<1>("h00") @[Core.scala 52:25]
    reg cycle_cnt : UInt<64>, clock with : (reset => (reset, UInt<64>("h00"))) @[Core.scala 54:26]
    reg instr_cnt : UInt<64>, clock with : (reset => (reset, UInt<64>("h00"))) @[Core.scala 55:26]
    node _cycle_cnt_T = add(cycle_cnt, UInt<1>("h01")) @[Core.scala 57:26]
    node _cycle_cnt_T_1 = tail(_cycle_cnt_T, 1) @[Core.scala 57:26]
    cycle_cnt <= _cycle_cnt_T_1 @[Core.scala 57:13]
    node _instr_cnt_T = add(instr_cnt, UInt<1>("h01")) @[Core.scala 58:26]
    node _instr_cnt_T_1 = tail(_instr_cnt_T, 1) @[Core.scala 58:26]
    instr_cnt <= _instr_cnt_T_1 @[Core.scala 58:13]
    wire rf_a0 : UInt<64>
    rf_a0 <= UInt<64>("h00")
    inst dt_te of DifftestTrapEvent @[Core.scala 63:21]
    dt_te.instrCnt is invalid
    dt_te.cycleCnt is invalid
    dt_te.pc is invalid
    dt_te.code is invalid
    dt_te.valid is invalid
    dt_te.coreid is invalid
    dt_te.clock is invalid
    dt_te.clock <= clock @[Core.scala 64:21]
    dt_te.coreid <= UInt<1>("h00") @[Core.scala 65:21]
    node _dt_te_io_valid_T = eq(fetch.io.inst, UInt<7>("h06b")) @[Core.scala 66:39]
    dt_te.valid <= _dt_te_io_valid_T @[Core.scala 66:21]
    node _dt_te_io_code_T = bits(rf_a0, 2, 0) @[Core.scala 67:29]
    dt_te.code <= _dt_te_io_code_T @[Core.scala 67:21]
    dt_te.pc <= fetch.io.pc @[Core.scala 68:21]
    dt_te.cycleCnt <= cycle_cnt @[Core.scala 69:21]
    dt_te.instrCnt <= instr_cnt @[Core.scala 70:21]
    inst dt_cs of DifftestCSRState @[Core.scala 72:21]
    dt_cs.medeleg is invalid
    dt_cs.mideleg is invalid
    dt_cs.sscratch is invalid
    dt_cs.mscratch is invalid
    dt_cs.mie is invalid
    dt_cs.mip is invalid
    dt_cs.satp is invalid
    dt_cs.scause is invalid
    dt_cs.mcause is invalid
    dt_cs.stvec is invalid
    dt_cs.mtvec is invalid
    dt_cs.stval is invalid
    dt_cs.mtval is invalid
    dt_cs.sepc is invalid
    dt_cs.mepc is invalid
    dt_cs.sstatus is invalid
    dt_cs.mstatus is invalid
    dt_cs.priviledgeMode is invalid
    dt_cs.coreid is invalid
    dt_cs.clock is invalid
    dt_cs.clock <= clock @[Core.scala 73:27]
    dt_cs.coreid <= UInt<1>("h00") @[Core.scala 74:27]
    dt_cs.priviledgeMode <= UInt<2>("h03") @[Core.scala 75:27]
    dt_cs.mstatus <= UInt<1>("h00") @[Core.scala 76:27]
    dt_cs.sstatus <= UInt<1>("h00") @[Core.scala 77:27]
    dt_cs.mepc <= UInt<1>("h00") @[Core.scala 78:27]
    dt_cs.sepc <= UInt<1>("h00") @[Core.scala 79:27]
    dt_cs.mtval <= UInt<1>("h00") @[Core.scala 80:27]
    dt_cs.stval <= UInt<1>("h00") @[Core.scala 81:27]
    dt_cs.mtvec <= UInt<1>("h00") @[Core.scala 82:27]
    dt_cs.stvec <= UInt<1>("h00") @[Core.scala 83:27]
    dt_cs.mcause <= UInt<1>("h00") @[Core.scala 84:27]
    dt_cs.scause <= UInt<1>("h00") @[Core.scala 85:27]
    dt_cs.satp <= UInt<1>("h00") @[Core.scala 86:27]
    dt_cs.mip <= UInt<1>("h00") @[Core.scala 87:27]
    dt_cs.mie <= UInt<1>("h00") @[Core.scala 88:27]
    dt_cs.mscratch <= UInt<1>("h00") @[Core.scala 89:27]
    dt_cs.sscratch <= UInt<1>("h00") @[Core.scala 90:27]
    dt_cs.mideleg <= UInt<1>("h00") @[Core.scala 91:27]
    dt_cs.medeleg <= UInt<1>("h00") @[Core.scala 92:27]
    
  extmodule ram_2r1w : 
    input clk : Clock
    input imem_en : UInt<1>
    input imem_addr : UInt<64>
    output imem_data : UInt<32>
    input dmem_en : UInt<1>
    input dmem_addr : UInt<64>
    output dmem_rdata : UInt<64>
    input dmem_wdata : UInt<64>
    input dmem_wmask : UInt<64>
    input dmem_wen : UInt<1>
    
    defname = ram_2r1w
    
    
  module Ram2r1w : 
    input clock : Clock
    input reset : Reset
    output io : {flip imem : {en : UInt<1>, addr : UInt<64>, flip rdata : UInt<64>}, flip dmem : {en : UInt<1>, addr : UInt<64>, flip rdata : UInt<64>, wdata : UInt<64>, wmask : UInt<64>, wen : UInt<1>}}
    
    inst mem of ram_2r1w @[Ram.scala 37:19]
    mem.dmem_wen is invalid
    mem.dmem_wmask is invalid
    mem.dmem_wdata is invalid
    mem.dmem_rdata is invalid
    mem.dmem_addr is invalid
    mem.dmem_en is invalid
    mem.imem_data is invalid
    mem.imem_addr is invalid
    mem.imem_en is invalid
    mem.clk is invalid
    mem.clk <= clock @[Ram.scala 38:21]
    mem.imem_en <= io.imem.en @[Ram.scala 39:21]
    mem.imem_addr <= io.imem.addr @[Ram.scala 40:21]
    io.imem.rdata <= mem.imem_data @[Ram.scala 41:21]
    mem.dmem_en <= io.dmem.en @[Ram.scala 42:21]
    mem.dmem_addr <= io.dmem.addr @[Ram.scala 43:21]
    io.dmem.rdata <= mem.dmem_rdata @[Ram.scala 44:21]
    mem.dmem_wdata <= io.dmem.wdata @[Ram.scala 45:21]
    mem.dmem_wmask <= io.dmem.wmask @[Ram.scala 46:21]
    mem.dmem_wen <= io.dmem.wen @[Ram.scala 47:21]
    
  module SimTop : 
    input clock : Clock
    input reset : UInt<1>
    output io : {logCtrl : {flip log_begin : UInt<64>, flip log_end : UInt<64>, flip log_level : UInt<64>}, perfInfo : {flip clean : UInt<1>, flip dump : UInt<1>}, uart : {out : {valid : UInt<1>, ch : UInt<8>}, in : {valid : UInt<1>, flip ch : UInt<8>}}}
    
    inst core of Core @[SimTop.scala 12:20]
    core.clock <= clock
    core.reset <= reset
    inst mem of Ram2r1w @[SimTop.scala 14:19]
    mem.clock <= clock
    mem.reset <= reset
    core.io.imem.rdata <= mem.io.imem.rdata @[SimTop.scala 15:15]
    mem.io.imem.addr <= core.io.imem.addr @[SimTop.scala 15:15]
    mem.io.imem.en <= core.io.imem.en @[SimTop.scala 15:15]
    mem.io.dmem.wen <= core.io.dmem.wen @[SimTop.scala 16:15]
    mem.io.dmem.wmask <= core.io.dmem.wmask @[SimTop.scala 16:15]
    mem.io.dmem.wdata <= core.io.dmem.wdata @[SimTop.scala 16:15]
    core.io.dmem.rdata <= mem.io.dmem.rdata @[SimTop.scala 16:15]
    mem.io.dmem.addr <= core.io.dmem.addr @[SimTop.scala 16:15]
    mem.io.dmem.en <= core.io.dmem.en @[SimTop.scala 16:15]
    io.uart.out.valid <= UInt<1>("h00") @[SimTop.scala 18:21]
    io.uart.out.ch <= UInt<1>("h00") @[SimTop.scala 19:18]
    io.uart.in.valid <= UInt<1>("h00") @[SimTop.scala 20:20]
    
